[1]崔冰,杨骁,徐锦里.低抖动高线性压控振荡器设计与仿真分析[J].华侨大学学报(自然科学版),2017,38(6):858-861.[doi:10.11830/ISSN.1000-5013.201509027]
 CUI Bing,YANG Xiao,XU Jinli.Design and Simulation Analysis of Low-Jitter High-Linearity Voltage-Controlled Oscillator[J].Journal of Huaqiao University(Natural Science),2017,38(6):858-861.[doi:10.11830/ISSN.1000-5013.201509027]
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低抖动高线性压控振荡器设计与仿真分析()
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《华侨大学学报(自然科学版)》[ISSN:1000-5013/CN:35-1079/N]

卷:
第38卷
期数:
2017年第6期
页码:
858-861
栏目:
出版日期:
2017-11-20

文章信息/Info

Title:
Design and Simulation Analysis of Low-Jitter High-Linearity Voltage-Controlled Oscillator
文章编号:
1000-5013(2017)06-0858-04
作者:
崔冰12 杨骁12 徐锦里12
1. 华侨大学 信息科学与工程学院, 福建 厦门 361021; 2. 厦门市ASIC与系统重点实验室, 福建 厦门 361008
Author(s):
CUI Bing12 YANG Xiao12 XU Jinli12
1. College of Information Science and Engineering, Huaqiao University, Xiamen 361021, China2. Key Laboratory of ASIC and System of Xiamen, Xiamen 361008, China
关键词:
锁相环 压控振荡器 浮空电容 相位噪声
Keywords:
phase-locked loop voltage-controlled oscillator floating timing capacitor phase noise
分类号:
TN752.1
DOI:
10.11830/ISSN.1000-5013.201509027
文献标志码:
A
摘要:
设计一种应用于锁相环(PLL)电路的压控振荡器(VCO).该电路采用浮空电容结构,相对传统接地电容结构,可提高电容充放电幅值,减小时钟抖动.快速电平检测电路,使电路在未采用反馈和补偿的前提下,减小环路延时,从而实现高线性.电路采用CSMC 0.6 μm CMOS标准工艺库实现.仿真结果表明:振荡频率为0.79,24,30 MHz时的相位噪声达到-128,-122,-120 dBc·Hz-1@1 MHz.通过调节外接电阻电容,使得电路在3~6 V电源电压下,输出100.0~3.0×107 MHz的矩形波,电路兼具低相位噪声和高线性特性.
Abstract:
A voltage-controlled oscillator(VCO)was designed for phase-locked loop(PLL). Floating timing capacitor architecture was adopted to enhance amplitude of capacitor’s charge and discharge, compared with grounded timing capacitor architecture, reducing the clock jitter. The rapid level detection circuit, which reduced the loop delay and achieves high-linearity without using feedback and compensation. The circuit was designed in CSMC 0.6 μm CMOS process. Simulation results showed that the phase noise was -128, -122, -120 dBc·Hz-1@1 MHz when the oscillation frequency was 0.79, 24, 30 MHz. The circuit output 100.0~3.0×107 Hz square wave at 3~6 V supply voltage by adjusting the external resistor and capacitor. The characters of this circuit were not only low phase noise but also high-linearity.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期: 2015-09-20
通信作者: 杨骁(1978-),男,讲师,博士,主要从事模拟集成电路设计的研究.E-mail:xiaoyanghqu@hqu.edu.cn.
基金项目: 福建省科技计划重点项目(2013H0029); 福建省泉州市科技计划项目(2013Z33); 华侨大学研究生科研创新能力培育计划资助项目(1400201019)
更新日期/Last Update: 2017-11-20