[1]傅文渊,凌朝东.CMOS全差分跨导运算放大器的建模与设计[J].华侨大学学报(自然科学版),2012,33(1):23-26.[doi:10.11830/ISSN.1000-5013.2012.01.0023]
　FU Wen-yuan,LING Chao-dong.Design and Modeling of a CMOS Fully Differential Transconductance Operational Amplifier[J].Journal of Huaqiao University(Natural Science),2012,33(1):23-26.[doi:10.11830/ISSN.1000-5013.2012.01.0023]
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CMOS全差分跨导运算放大器的建模与设计()
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《华侨大学学报（自然科学版）》[ISSN:1000-5013/CN:35-1079/N]

卷:
第33卷
期数:
2012年第1期
页码:
23-26
栏目:
出版日期:
2012-01-20

文章信息/Info

Title:
Design and Modeling of a CMOS Fully Differential Transconductance Operational Amplifier
文章编号:
1000-5013(2012)01-0023-04
作者:
傅文渊; 凌朝东
华侨大学信息科学与工程学院; 厦门市专用集成电路系统重点实验室
Author(s):
FU Wen-yuan1; 2;  LING Chao-dong1; 2
1.College of Information Science and Engineering, Huaqiao University, Xiamen 361021, China; 2.Key Laboratory of ASIC and System of Xiamen, Xiamen 361008, China
关键词:
运算放大器;  全差分跨导;  增益自举;  模数转换器;  互补金属氧化物半导体
Keywords:
operational amplifier;  fully differential transconductance;  gain-boosting;  analog to digital converter;  complementary metal-oxide-semiconductor
分类号:
TN722.77
DOI:
10.11830/ISSN.1000-5013.2012.01.0023
文献标志码:
A
摘要:
研究带增益自举结构的高速、高增益跨导运算放大器,并对增益自举运放建立数学模型和进行Mat-lab仿真验证.将设计的运算放大器应用于12bit 100MSPS模数转换器(ADC)中,可得到辅助运放的带宽的最佳设计.仿真结果表明:添加辅助运放后,可以达到106dB的增益,增加了55dB; 添加辅助运放后的主极点较之前大大减小,次主极点略有减小,但辅助运放的添加并不会影响运放使用时的速度.
Abstract:
Research of high-speed and high-gain transconductance amplifier with the structure of gain-boost,the mathematical modeling and Matlab simulation is presented for gain-boost operational amplifier.Designed operational amplifier is used in 12 bit 100 M SPSADC,and the optimal design on the auxiliary amplifier bandwidth can be obtained.Simulation results show that gain is 106 dB which increses of 55 dB if an auxiliary operational amplifier is added.Besides,if we the auxiliary operational,dominant pole is greatly reduced and non-dominant pole slightly decreases,but the addition of auxiliary amplifier does not affect the speed of the operational amplifier.

参考文献/References:

[1] GALTON S E. A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC [J]. IEEE Journal of Solid-State Circuits, 2004, (12):2126-2138.doi:10.1109/JSSC.2004.836230.
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[7] 凌朝东, 黄群峰, 张艳红. 脑电信号提取专用电极芯片的设计 [J]. 华侨大学学报(自然科学版), 2007(3):260-263.doi:10.3969/j.issn.1000-5013.2007.03.010.

备注/Memo

备注/Memo:
国家自然科学基金资助项目(60772164); 福建省自然科学基金资助项目(T0850005)
更新日期/Last Update: 2014-03-23