[1]朱坤旺,傅文渊,凌朝东.低功耗H.264 Baseline解码IP核设计[J].华侨大学学报(自然科学版),2011,32(3):280-283.[doi:10.11830/ISSN.1000-5013.2011.03.0280]
　ZHU Kun-wang,FU Wen-yan,LING Chao-dong.Design of Low-Power H.264 Baseline Decoder IP Core[J].Journal of Huaqiao University(Natural Science),2011,32(3):280-283.[doi:10.11830/ISSN.1000-5013.2011.03.0280]
点击复制

低功耗H.264 Baseline解码IP核设计()
分享到：

《华侨大学学报（自然科学版）》[ISSN:1000-5013/CN:35-1079/N]

卷:
第32卷
期数:
2011年第3期
页码:
280-283
栏目:
出版日期:
2011-05-20

文章信息/Info

Title:
Design of Low-Power H.264 Baseline Decoder IP Core
文章编号:
1000-5013(2011)03-0280-04
作者:
朱坤旺; 傅文渊; 凌朝东
华侨大学信息科学与工程学院; 厦门市专用集成电路系统重点实验室
Author(s):
ZHU Kun-wang1; 2;  FU Wen-yan1; 2;  LING Chao-dong1; 2
1.College of Information Science and Engineering, Huaqiao University, Quanzhou 362021, China; 2.Key Laboratory of ANSIC and System, Xiamen 361008, China
关键词:
H.264解码器;  IP核;  低功耗;  现场可编程门阵列
Keywords:
H.264 decoder;  IP core;  low-power;  field programmable gate array
分类号:
TN764
DOI:
10.11830/ISSN.1000-5013.2011.03.0280
文献标志码:
A
摘要:
采用环形码流缓冲结构、首"1"检测方法和优先级非均匀分割技术,设计一款低功耗H.264 Baseline视频解码IP核,并对该IP核进行了软件仿真和现场可编程门阵列(FPGA)验证.结果表明,该IP核的功耗为918μW,降低了44%,H.264/AVC Baseline QCIF解码速度达到30帧·s-1,可满足实时解码需求.
Abstract:
Using the structure with circular bitstream buffer and the first ’1’ detection method and priority non-uniform segmentation to design a low-power H.264 baseline video decoder IP core,and software simulation and field programmable gate array(FPGA) verification is investigated.The results show that the IP core′s power consumption is 918 μW,decreased 44%.H.264/AVC baseline QCIF decoding speed meet the needs of real-time decoding of 30·s-1.

备注/Memo

备注/Memo:
福建省自然科学基金资助项目(T0850005); 福建省厦门市科技计划项目(3502Z20080010)
更新日期/Last Update: 2014-03-23