[1]高银,林其伟.DDS数字移相正弦信号发生器的设计[J].华侨大学学报(自然科学版),2009,30(1):34-37.[doi:10.11830/ISSN.1000-5013.2009.01.0034]
　GAO Yin,LIN Qi-wei.The Design of DDS Digital Phase-Shift Sine Signal Generator[J].Journal of Huaqiao University(Natural Science),2009,30(1):34-37.[doi:10.11830/ISSN.1000-5013.2009.01.0034]
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DDS数字移相正弦信号发生器的设计()
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《华侨大学学报（自然科学版）》[ISSN:1000-5013/CN:35-1079/N]

卷:
第30卷
期数:
2009年第1期
页码:
34-37
栏目:
出版日期:
2009-01-20

文章信息/Info

Title:
The Design of DDS Digital Phase-Shift Sine Signal Generator
文章编号:
1000-5013(2009)01-0034-04
作者:
高银; 林其伟
华侨大学信息科学与工程学院
Author(s):
GAO Yin;  LIN Qi-wei
College of Information Science and Engineering, Huaqiao University, Quanzhou 362021, China
关键词:
直接数字频率合成器;  现场可编程门阵列;  信号发生器;  正弦信号;  数字移相
Keywords:
direct digital synthesizer;  field programmable gate array;  signal generator;  sine signal;  digital phase-shift
分类号:
TN74
DOI:
10.11830/ISSN.1000-5013.2009.01.0034
文献标志码:
A
摘要:
在直接数字频率合成器(DDS)的基础上,利用现场可编程门阵列(FPGA)设计一款数字移相正弦信号发生器,并通过Altera公司的DE2开发板来验证.在输入环节加入一个数据锁存器,用"软设置"替代"硬设置",同时在ROM的验证中只采样正弦波的正上半周,来代替整个周期的采样,以降低系统的设计规模,减少系统对逻辑资源的需求.最后,绘制数字移相正弦信号发生器的顶层电路图,在QUARTUS 6.0软件中进行仿真和硬件验证结果.
Abstract:
Based on direct digital synthesizer(DDS) and using field programmable gate array(FPGA),a digital phase-shift sine signal generator had been designed.This signal generator was verified through Altera Corporation′s DE2 develop board.In this design,a data flip-latch was added at the input side,the "soft setting" was employed instead of "hard setting".At the same time,and the positive half period sampling was used instead of the full period sampling of sine wave in the ROM verification,,the scale of system and the demand to the systemic logic resources were reduced.At the end,the top layer circuit diagram of digital phase-shift sine signal generator was drawn,and the hardware circuit was simulated on the Quareus 6.0.

参考文献/References:

[1] 潘松, 黄继业. EDA技术与VHDL [M]. 北京:清华大学出版社, 2005.388-396.
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[3] 黄飞, 鲁迎春, 何晓雄. 基于DDS的LFM信号发生器的FPGA设计 [J]. 合肥工业大学学报(自然科学版), 2006(5):617-619.doi:10.3969/j.issn.1003-5060.2006.05.027.
[4] 章小梅, 姜茂仁, 费元春. DDS杂散的抑制与研究 [J]. 信息技术, 2004(4):1-4.
[5] 邓成, 张亚妮, 白璘. 嵌入式逻辑分析仪在FPGA设计中的应用 [J]. 现代电子技术, 2006(2):76-84.doi:10.3969/j.issn.1004-373X.2006.02.030.

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备注/Memo

备注/Memo:
国务院侨办科研基金资助项目(06QZR03)
更新日期/Last Update: 2014-03-23