[1]李靖坤,杨骁,陈国晏,等.高速低功耗CMOS动态锁存比较器的设计[J].华侨大学学报(自然科学版),2018,39(4):618-622.[doi:10.11830/ISSN.1000-5013.201608011]
　LI Jingkun,YANG Xiao,CHEN Guoyan,et al.Design of High-Speed Low-Power CMOS Dynamic Latched Comparator[J].Journal of Huaqiao University(Natural Science),2018,39(4):618-622.[doi:10.11830/ISSN.1000-5013.201608011]
点击复制

高速低功耗CMOS动态锁存比较器的设计()
分享到：

《华侨大学学报（自然科学版）》[ISSN:1000-5013/CN:35-1079/N]

卷:
第39卷
期数:
2018年第4期
页码:
618-622
栏目:
出版日期:
2018-07-18

文章信息/Info

Title:
Design of High-Speed Low-Power CMOS Dynamic Latched Comparator
文章编号:
1000-5013(2018)04-0618-05
作者:
李靖坤1; 2;  杨骁1; 2;  陈国晏1; 2;  娄付军1; 2;  邱伟彬1; 2
1. 华侨大学 信息科学与工程学院, 福建 厦门 361021; 2. 厦门市ASIC与系统重点实验室, 福建 厦门 361008
Author(s):
LI Jingkun1; 2;  YANG Xiao1; 2;  CHEN Guoyan1; 2;  LOU Fujun1; 2;  QIU Weibin1; 2
1. College of Information Science and Engineering, Huaqiao University, Xiamen 361021, China; 2. Key Laboratory of ASIC and System of Xiamen, Xiamen 361008, China
关键词:
动态锁存比较器;  互补金属氧化物半导体;  高速低功耗;  失调电压
Keywords:
dynamic latched comparator;  complementary metal-oxide-semiconductor;  high-speed low-power;  offset voltage
分类号:
TN432
DOI:
10.11830/ISSN.1000-5013.201608011
文献标志码:
A
摘要:
提出一种高速低功耗动态锁存比较器,电路包含预放大器、锁存比较器和SR锁存器3部分.采用一种新的锁存比较器复位电路,该电路仅由一个P沟道金属氧化物半导体(PMOS)管构成,实现电荷的再利用,减小了延迟,降低了功耗.SR锁存器输入端口的寄生电容为锁存比较器的负载电容,对SR锁存器的输入端口进行改进,避免由于锁存比较器的负载电容失配导致的输入失调电压偏移的问题.电路采用TSMC 0.18 μm 互补金属氧化物半导体(CMOS)工艺实现.结果表明:电源电压为1.8 V,时钟频率为1 GHz时,比较器精度达0.3 mV;最大输入失调电压为8 mV,功耗为0.2 mW;该比较器具有电路简单易实现、功耗低的特点.
Abstract:
A high-speed low-power dynamic latched comparator including a pre-amplifier, a latched comparator and a SR-latch is presented. A novel reset circuit that only has one PMOS transistor is adopted for the latched comparator, which can realize the electric charge reusing. As a result, the delay and power consumption are reduced. The parasitic capacitance of input transistors of the SR-latch acts as the load capacitance of the latched comparator. An improved method for the SR-latch is adopted to avoid shifting of the input offset voltage caused by the load capacitance mismatch of the latched comparator. The comparator is implemented with TSMC 0.18 μm complementary metal-oxide-semiconductor(CMOS)technology. Simulation results show that a sensitivity of 0.3 mV and a maximum input offset of 8 mV are achieved with the operating frequency of 1 GHz, and the power consumption is 0.2 mW with 1.8 V supply. The dynamic latched comparator is concise and simple to implement, and has features of low power.

参考文献/References:

[1] SCHINKEL D,MENSINK E,KLUMPERINK E A M,et al.A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects[J].Journal of Solid-State Circuits,2006,41(1):297-306.
[2] SHEIKHAEI S,MIRABBASI S,IVANOV A.A 0.35 μm CMOS comparator circuit for high-speed ADC applications[C]//International Symposium on Circuits and Systems.Kobe:IEEE Press,2005:6134-6137.
[3] FAHMY G A,POKHAREL R K,KANAYA H,et al.A 1.2 V 246 μW CMOS latched comparator with neutralization technique for reducing kickback noise[C]//IEEE Region 10 Conference.Fukuoka:IEEE Press,2010:1162-1165.DOI:10.1109/TENCON.2010.5686392.
[4] 吴笑峰,刘红侠,石立春,等.新型高速低功耗CMOS动态比较器的特性分析[J].中南大学学报(自然科学版),2009,40(5):1354-1359.
[5] MIYAHARA M,ASADA Y,PAIK D,et al.A low-noise self-calibrating dynamic comparator for high-speed ADCs[C]//Asian Solid-State Circuits Conference.Fukuoka:IEEE Press,2008:269-272.
[6] JEON H J,KIM Y B.A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator[J].Analog Integrated Circuits and Signal Processing,2012,70(3):337-346.DOI:10.1007/s10470-011-9687-5.
[7] WONG K L J,YANG C K K.Offset compensation in comparators with minimum input-referred supply noise[J].Journal of Solid-State Circuits,2004,37(5):837-840.DOI:10.1109/JSSC.2004.826317.
[8] SCHINKEL D,MENSINK E,KLUMPERINK E,et al.A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time[C]//International Solid-State Circuits Conference.California:IEEE Press,2007:314-605.
[9] NIKOOZADEH A,MURMANN B.An analysis of latch comparator offset due to load capacitor mismatch[J].Transactions on Circuits and Systems Ⅱ: Express Briefs,2006,53(12):1398-1402.
[10] RAZAVI B,WOOLEY B A.Design techniques for high-speed, high-resolution comparators[J].Journal of Solid-State Circuits,1993,27(12):1916-1926.DOI:10.1109/4.173122.

相似文献/References:

[1]傅文渊,凌朝东.CMOS全差分跨导运算放大器的建模与设计[J].华侨大学学报(自然科学版),2012,33(1):23.[doi:10.11830/ISSN.1000-5013.2012.01.0023]
　FU Wen-yuan,LING Chao-dong.Design and Modeling of a CMOS Fully Differential Transconductance Operational Amplifier[J].Journal of Huaqiao University(Natural Science),2012,33(4):23.[doi:10.11830/ISSN.1000-5013.2012.01.0023]
[2]林丽芬,凌朝东,杨骁.CMOS宽带低噪声放大器的设计[J].华侨大学学报(自然科学版),2012,33(6):640.[doi:10.11830/ISSN.1000-5013.2012.06.0640]
　LIN Li-fen,LING Chao-dong,YANG Xiao.Design of Low Noise Amplifier in Wide-Band CMOS[J].Journal of Huaqiao University(Natural Science),2012,33(4):640.[doi:10.11830/ISSN.1000-5013.2012.06.0640]

备注/Memo

备注/Memo:
收稿日期: 2016-08-08
通信作者: 杨骁(1978-),男,讲师,博士,主要从事模拟集成电路设计的研究.E-mail:xiaoyanghqu@hqu.edu.cn.
基金项目: 福建省科技计划重点项目(2013H0029); 福建省泉州市科技计划项目(2013Z33); 华侨大学研究生科研创新能力培育计划资助项目(1511301027)
更新日期/Last Update: 2018-07-20