[1]崔冰,杨骁,娄付军,等.应用于锁相环中的锁定检测电路设计[J].华侨大学学报(自然科学版),2018,39(3):457-460.[doi:10.11830/ISSN.1000-5013.201605104]
　CUI Bing,YANG Xiao,LOU Fujun,et al.Design of Lock Detection Circuit for Phase-Locked Loop Applications[J].Journal of Huaqiao University(Natural Science),2018,39(3):457-460.[doi:10.11830/ISSN.1000-5013.201605104]
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应用于锁相环中的锁定检测电路设计()
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《华侨大学学报（自然科学版）》[ISSN:1000-5013/CN:35-1079/N]

卷:
第39卷
期数:
2018年第3期
页码:
457-460
栏目:
出版日期:
2018-05-20

文章信息/Info

Title:
Design of Lock Detection Circuit for Phase-Locked Loop Applications
文章编号:
1000-5013(2018)03-0457-04
作者:
崔冰1; 2;  杨骁1; 2;  娄付军1; 2;  邱伟彬1; 2
1. 华侨大学 信息科学与工程学院, 福建 厦门 361021; 2. 厦门市ASIC与系统重点实验室, 福建 厦门 361008
Author(s):
CUI Bing1; 2;  YANG Xiao1; 2;  LOU Fujun1; 2;  QIU Weibin1; 2
1. College of Information Science and Engineering, Huaqiao University, Xiamen 361021, China; 2. Key Laboratory of ASIC and System of Xiamen, Xiamen 361008, China
关键词:
锁相环;  锁定检测电路;  移位寄存器;  正反馈;  复位
Keywords:
phase-locked loop;  lock detection circuit;  shift register;  positive feedback;  reset
分类号:
TN47
DOI:
10.11830/ISSN.1000-5013.201605104
文献标志码:
A
摘要:
设计一种应用于锁相环(PLL)中的锁定检测电路(LDC).该电路采用移位寄存器的方式,当连续18个时钟周期内检测到锁定时,输出通过正反馈置为高电平.同时,在该电路中加入复位及强制锁定端口,采用SMIC 28 nm CMOS标准工艺库实现.仿真结果表明:当电源电压为0.9 V,参考频率在10~100 MHz范围内时,均可完成锁定检测.
Abstract:
A lock detection circuit(LDC)was developed for using in phase-locked loop(PLL). A shift register was used in this circuit, and the output was at high level through positive feedback when the lock was detected during 18 consecutive clock cycles. Meanwhile, reset and force locking ports were added in the circuit. The circuit was designed in SMIC 28 nm CMOS process. The results of simulation showed that the lock detection could be completed when the supply voltage was 0.9 V and the reference frequency was 10-100 MHz.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期: 2016-05-29
通信作者: 杨骁(1978-),男,讲师,博士,主要从事模拟集成电路设计的研究.E-mail:xiaoyanghqu@hqu.edu.cn.
基金项目: 福建省科技计划重点项目(2013H0029); 福建省泉州市科技计划项目(2013Z33); 华侨大学研究生科研创新能力培育计划资助项目(1400201019)
更新日期/Last Update: 2018-05-20