[1]陈燕.低密度奇偶校验码在数字信号处理器上的实现[J].华侨大学学报(自然科学版),2010,31(2):166-169.[doi:10.11830/ISSN.1000-5013.2010.02.0166]
　CHEN Yan.Implementation of an LDPC on DSP[J].Journal of Huaqiao University(Natural Science),2010,31(2):166-169.[doi:10.11830/ISSN.1000-5013.2010.02.0166]
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低密度奇偶校验码在数字信号处理器上的实现()
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《华侨大学学报（自然科学版）》[ISSN:1000-5013/CN:35-1079/N]

卷:
第31卷
期数:
2010年第2期
页码:
166-169
栏目:
出版日期:
2010-03-20

文章信息/Info

Title:
Implementation of an LDPC on DSP
文章编号:
1000-5013(2010)02-0166-04
作者:
陈燕
华侨大学信息科学与工程学院
Author(s):
CHEN Yan
College of Information Science and Engineering, Huaqiao University, Quanzhou 362021, China
关键词:
低密度奇偶校验码;  数字信号处理器;  译码;  校验
Keywords:
low-density parity-check codes;  digital signal processor;  decoding;  checking
分类号:
TN911.2
DOI:
10.11830/ISSN.1000-5013.2010.02.0166
文献标志码:
A
摘要:
研究低密度奇偶校验码(LDPC)的数字信号处理实现,并采用TMS320C5409DSP芯片进行算法实现.优化和积算法中的具体运算,调整译码顺序,将硬判决放入变量节点中运算,校验和放入校验节点运算中,避免重复寻址,给出与现场可编程门阵列的通信方法.在时钟频率为20 MHz,译码迭代次数为10次时,测试得到的速率为20.4 kbit.s-1.
Abstract:
This paper has done some research on the implementation of an LDPC decoder on DSP and adopted TMS320C5409 DSP.The sum-product algorithm was optimized and the decoding order was rearranged.The hard decision was calculated in variable nodes and the check sum was calculated in check nodes to avoid repetitive addressing.The method to communicate with FPGA was presented.This decoder is able to decode at 20.4 kbit·s-1 on a TMS320C5409 DSP running at 20 MHz.

参考文献/References:

[1] MACKAY D J C, NEAL R M. Near shannon limit performance of low-density parity-check codes [J]. Electronics Letters, 1996, (18):1645-1646.
[2] HU X Y, ELEFTHERIOU E, ARNOLD D M. Regular and irregular progressive edge-growth tanner graphs [J]. Information Theory, 2005(1):386-398.doi:10.1109/TIT.2004.839541.
[3] CHEN Jing-hu, TANNER R M, JONES C. Improved min-sum decoding algorithms for irregular LDPC codes [A]. 2005.449-453.
[4] LECHNER G, SAYIR J, RUPP M. Efficient DSP implementation of an LDPC decoder [A]. 2004.665-668.

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备注/Memo

备注/Memo:
华侨大学科研基金资助项目(08HZR15)
更新日期/Last Update: 2014-03-23